What is the specific protocol of QSPI?

Winbond's W25X family supports Dual-SPI, effectively doubling standard SPI clock rates. The W25Q family is a "superset" of the 25X family with Dual-I/O and Quad-I/O SPI for even higher performance. Clock rates up to 104MHz achieve an equivalent of 416MHz (50M-Byte/S transfer rate) when using Quad-SPI. This is more than four times the performance of ordinary Serial Flash (50MHz) and even surpasses asynchronous Parallel Flash memories while using fewer pins and less space.    

Faster transfer rates mean controllers can execute code with Execute in Place methods (XIP) directly from the SPI interface or further improve boot time when shadowing code to RAM.    

Some SpiFlash® devices offer the new Quad Peripheral Interface (QPI) supporting true Quad Commands for improved XIP performance and simpler controller circuitry. Additionally, new ultra-small form factor packages are ideal for space constrained mobile and handheld applications.

1. What is SPI and QSPI? 

Their similarities and differences

The SPI protocol actually includes three protocol interfaces: Standard SPI, Dual SPI and Queued SPI, corresponding to 3-wire, 4-wire and 6-wire respectively.

(1) Usually what we call SPI is Standard SPI, which has 4 signal lines, namely CLK, CS, MOSI and MISO. The data line operates in full duplex.

(2) Dual SPI, it is only for SPI Flash, not for all SPI peripherals. For SPI Flash, full-duplex is not commonly used, so the usage of mosi and miso is expanded to let them work in half-duplex to double the data transmission. That is to say, for Dual SPI Flash, you can send a command byte to enter dual mode, so that mosi becomes SIO0 (serial io 0), mosi becomes SIO1 (serial io 1), so that 2 bits of data can be transmitted in one clock cycle , doubling the data transfer.

(3) Similar, it can also be expanded. Also for SPI Flash, Qual SPI Flash adds two I/O lines (SIO2, SIO3), with the purpose of transmitting 4 bits in one clock.

QSPI is the abbreviation of Queued SPI.

2. Interface problem

The picture above is a schematic diagram of the pin interface of a certain SPI FLASH. It supports SPI communication, and can also use DSPI communication or QSPI communication.

This chip has a total of 8 useful pins, and the function of each pin is defined as follows:

A detailed description of each pin is as follows:

1. Chip Select(/CS)

       The function of the chip select signal Chip Select (/CS) is to enable or disable the operation of the device. When CS is high, it means that the device is not selected. The serial data output line (DO or IO0, IO1, IO2, IO3) All are in a high-impedance state. When CS is low, it means that the device is selected, and the FPGA can send data to or receive data from QSPI Flash.

2. Serial data input signal DI and serial output signal DO

       The standard SPI protocol stores the data on the serial input signal DI into QSPI Flash on the rising edge of the serial clock signal (SCLK), and serializes the data in QSPI Flash on the falling edge of the serial clock signal (SCLK). Output via unidirectional DO pin. In Dual SPI and Quad SPI, DI and DO are bidirectional signals (can be used as input or output).

3. Write Project(/WP)

       The function of the write protection signal is to prevent the QSPI Flash status register from being written with wrong data. The WP signal is active at low level, but when the QE bit of status register 2 is set to 1, the WP signal loses the write protection function and it becomes Quad A bidirectional data transfer signal of SPI.

4. HOLD(/HOLD)

      The function of the HOLD signal is to suspend the operation of QSPI Flash. When the HOLD signal is low and CS is also low, the serial output signal DO will be in a high-impedance state, and the serial input signal DI and the serial clock signal SCLK will be ignored by the QSPI Flash. When HOLD is pulled high, the read and write operations of QSPI Flash can continue. When multiple SPI devices share the same signal of the same SPI bus, the signal flow direction can be switched through HOLD. Like the WP signal, when the QE bit of status register 2 is set to 1, the HOLD signal loses its holding function and it also becomes a bidirectional data transmission signal of Quad SPI.

5. Serial clock line

      The serial clock line is used to provide the clock for serial input and output operations.

3. Use of QSPI

3.1 Working mode

The interface can work in the following three modes:

① Indirect mode: use QSPI register to perform all operations

② Status polling mode: The external Flash status register is read periodically, and an interrupt will be generated when the flag position is 1 (if erasing or programming is completed, an interrupt will be generated)

③ Memory mapping mode: The external Flash is mapped to the microcontroller address space, so that the system treats it as internal memory

When using dual-flash mode, two Quad-SPI Flashes will be accessed at the same time, and the throughput and capacity can be increased by two times.

QSPI functional block diagram, dual flash mode disabled:

QSPI uses 6 signals to connect to Flash, namely four data lines BK1_IO0~BK1_IO3, a clock output CLK, and a chip select output (active low level) BK1_nCS. Their functions are introduced as follows:

● BK1_nCS: Chip select output (active low level), suitable for FLASH 1. If QSPI is always operated in dual flash mode, it can also be used for the FLASH 2 slave select signal line. QSPI communication starts with the BK1_nCS line being driven low, and ends with the BK1_nCS line being pulled high.

● CLK: Clock output, suitable for two memories, used for communication data synchronization. It is generated by the communication host and determines the communication rate. Different devices support different maximum clock frequencies. For example, the maximum QSPI clock frequency of STM32 is fpclk/2. When communicating between two devices, the communication rate is limited by the low-speed device. .

● BK1_IO0: Bidirectional IO in dual/four-wire mode, serial output in single-wire mode, suitable for FLASH 1.

● BK1_IO1: Bidirectional IO in dual/four-wire mode, serial input in single-wire mode, suitable for FLASH 1.

● BK1_IO2: Bidirectional IO in four-wire mode, suitable for FLASH 1.

● BK1_IO3: Bidirectional IO in four-wire mode, suitable for FLASH 1.

3.2 Status

We can choose which method to use to communicate with it through configuration. Before performing a four-wire read and write operation (QSPI), the QE (Quad Enable) bit in the register must be set to 1. In addition, the four-wire read operation also needs to wait for 8 dummy clocks before reading data to speed up the reading of data. Speed (please read the chip manual for details). Therefore, compared with single-wire operation, in addition to adding the status of reading and writing data in four-wire mode, four-wire operation also needs to add a write status register function to turn on the QE (Quad Enable) bit and a dummy to wait for 8 clocks. .

The status of four-wire mode is as follows:

1. Idle state: used to initialize the values of each register

2. Send command status: used to send 8-bit command code

3. Sending address status: used to send 24-bit address code

4. Read waiting state (single-wire mode): When the data reading operation is in progress, enter this state and wait for the completion of reading data.

5. Write data state (single-wire mode): In this state, the FPGA writes data to the QSPI Flash.

6. Write status register status: used to set QE (Quad Enable) of the status register to 1

7. Dummy Clock status: You need to wait for 8 dummy clocks before reading data on four lines

8. Write data state (four-wire mode): In this state, the FPGA writes data to the QSPI Flash through the four-wire mode.

9. Read waiting state (four-wire mode): In this state, wait for the FPGA to complete reading data from QSPI Flash through four-wire mode.

10. End status: An instruction operation ends and an end flag is given.

Among them, states 6-9 are the four states added by the four-wire mode code on the basis of the single-wire mode code.

3.3 Command sequence

QSPI communicates with Flash through commands. Each command includes five stages: instruction, address, alternating (multiplexed) byte, null instruction and data. Any of these five stages can be skipped, but at least it must contain instructions. , address, alternate byte or one of the data phases. nCS falls before each instruction starts and rises again after each instruction completes. The read command timing in QSPI four-wire mode is shown in the figure below.

1) Instruction phase

At this stage, an 8-bit instruction configured in the instruction field of the QSPI_CCR[7:0] register is sent to Flash to specify the type of operation to be performed.

Although most flashes can only receive instructions 1 bit at a time from the IO0/SO signal (single-wire SPI mode), the instruction stage has the option of sending 2 bits at a time (via IO0/IO1 in dual-wire SPI mode) or 4 bits at a time. bits (via IO0/IO1/IO2/IO3 in Quad SPI mode). This is configurable via the IMODE[1:0] fields in the QSPI_CCR[9:8] register. If IMODE = 00, the instruction phase is skipped and the command sequence starts with the address phase (if present).

2)Address stage

In the address stage, 1-4 bytes are sent to Flash indicating the operation address. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of the QSPI_CCR[13:12] register. In indirect mode and automatic polling mode, the address byte to be sent is specified in ADDRESS[31:0] of the QSPI_AR register; in memory mapped mode, the address is given directly through AHB (from the kernel or DMA). The address stage can send 1 bit at a time (via SO in single-wire SPI mode), 2 bits (via IO0/IO1 in dual-wire SPI mode), or 4 bits (via IO0/IO1/IO2/IO3 in quad-wire SPI mode). This is configurable via the ADMODE[1:0] fields in the QUADSPI_CCR[11:10] register. If ADMODE = 00, the address phase is skipped and the command sequence goes directly to the next phase (if it exists).

3) Alternate byte phase

In the alternating byte stage, bytes 1-4 are sent to Flash, generally used to control the operating mode. The number of alternating bytes to be sent is configured in the ABSIZE[1:0] field of the QSPI_CCR[17:16] register. The bytes to be sent are specified in the QSPI_ABR register.

The alternating byte phase can send 1 bit (via SO in single-wire SPI mode), 2-bits (via IO0/IO1 in dual-wire SPI mode) or 4-bits (via IO0/IO1/IO2/ in quad-SPI mode) at a time. IO3). This is configurable via the ABMODE[1:0] fields in the QSPI_CCR[15:14] register. If ABMODE = 00, the alternating byte phase is skipped and the command sequence proceeds directly to the next phase (if it exists).

There are situations during the Alternate Byte phase when only a single nibble is sent instead of a full byte, such as when dual-wire mode is used and only two cycles are used to send the Alternate Byte. In this case, the firmware can assume Quad mode (ABMODE = 11) and send a byte by setting bits 7 and 3 of ALTERNATE to "1" (IO3 remains high) and setting bits 6 and 2 to "0" ” (the IO2 line remains low). At this time, the upper 2 bits of the nibble are stored in bits 4:3 of ALTERNATE, and the lower 2 bits are stored in bits 1 and 0. For example, if nibble 2 (0010) is sent over IO0/IO1, ALTERNATE should be set to 0x8A (1000_1010).

4) Empty instruction cycle phase

In the empty instruction cycle phase, no data is sent or received within a given 1-31 cycle. The purpose is to leave time for the Flash to prepare the data phase when a higher clock frequency is used. The number of cycles given in this phase is specified in the DCYC[4:0] field of the QSPI_CCR[22:18] register. In SDR and DDR modes, the duration is specified as a certain number of full clock cycles. If DCYC is zero, the empty instruction cycle phase is skipped and the command sequence directly enters the data phase (if it exists). The operating mode of the empty instruction cycle phase is determined by DMODE. In order to ensure that there is sufficient "turnaround" time for the data signal to change from output mode to input mode, when using dual-wire and four-wire modes to receive data from Flash, at least one empty instruction cycle needs to be specified.

5)Data stage

During the data phase, any number of bytes can be received from or sent to Flash. In indirect mode and auto-polling mode, the number of bytes to be sent/received is specified in the QSPI_DLR register. In indirect write mode, the data sent to Flash must be written to the QSPI_DR register. In indirect read mode, the data received from Flash is obtained by reading the QSPI_DR register. In memory mapped mode, the read data is sent directly back to the Cortex or DMA via the AHB. The data stage can send/receive 1 bit (via SO in single-wire SPI mode), 2-bit (via IO0/IO1 in dual-wire SPI mode) or 4-bits (via IO0/IO1/IO2/ in quad-SPI mode) at a time IO3). This is configurable via the ABMODE[1:0] fields in the QUADSPI_CCR[15:14] register. If DMODE = 00, the data phase is skipped and the command sequence is completed immediately when nCS is pulled high. This configuration is only available in indirect write-only mode.